Dynamic microscale flow patterning using electrical modulation of zeta potential

Significance Traditional microfluidic devices make use of physical channels and mechanical actuators, in which geometries and functionalities are intimately related to one another, i.e., changing the flow field requires change at the mechanical level. In this work, we introduce a concept in which a microfluidic chamber with no preset structures or active mechanical components can be dynamically configured to produce desired flow fields.

The images showing the experimental streamlines are obtained by superposition of multiple frames after background subtraction. Because the fluorescence intensity in the gate electrode regions is ~ 50 % less than elsewhere, we amplified the signal coming from the electrode regions by a factor of 2 to obtain a uniform signal on the entire image. We then inverted the color of the fluorescence images so that the particles appear in black over a white background. For the velocity measurement ( Fig. 1 D and Fig. 3) and for obtaining the vector map in Fig. 1 E and F, we analyze a series of sequential frames using PIVlab (1, 2).   We define the metal structures by a lift-off process, depositing a sandwiched metal layer of 2 nm Ti -2 nm Pt -2 nm Ti by physical evaporation (BAK501, Evatec AG). We use the two layers of titanium to improve the adhesion of the metal layers to both the substrate and the dielectric; the platinum layer is used because it is resistant to hydrofluoric acid (HF) and acts as a stopping layer during the etching process for opening the electrical connections. The metal layer thickness is 6 nm, thin enough to allow optical transmittance in the visible spectrum, enabling visualization of fluorescent beads using an inverted epifluorescence microscopy.

Device fabrication
We deposit 500 nm of silicon oxynitride (SiON) followed by 100 nm of silicon dioxide (SiO2) as dielectric layer by plasma-enhanced chemical vapor deposition (PECVD). To test different dielectric materials (see section 'System design and characterization' in the main text and Fig. S8 for more details) we use either PECVD, for SiO2, SiON and silicon nitride (SiNx), or atomic layer deposition (ADL), for SiO2, hafnium dioxide (HfO2) and aluminum oxide (Al2O3). We then expose the electrical contact by etching the dielectric over the driving electrodes and the pads by using HF (for SiO2, SiON, HfO2 and Al2O3) or dry etching for SiNx.
We deposit a 15 µm-thick layer of SU8 (SU8 3010, MicroChem Corp.) by spinning it for 40 s at 1500 rpm, and define the lateral walls of the micofluidic structure by a standard lithoghrapic step. Importantly, during all thermal steps (soft-and post-baking) for the SU8 treatment we do not elevate the temperature above 95 ˚C to keep residual epoxy groups active (3). We dice the wafer to singulate the devices with dimensions of approximately 2 × 1 cm.
We produce PDMS (Sylgard 184, Dow Corning) slabs of approximately 1 cm using a cross-linker to monomer ratio of 1:10 and cure it at 60°C for 3 h. We create the reservoirs by punching through the PDMS using standard circular biopsy punches (1 to 4 mm diamater). Finally, we treat the PDMS with air plamsa at 100 W for 30 s, place it in contact with the SU8 and bake at 140 ˚C to ensure a permanent bonding.
Both the driving and gate potentials were generated by one ore more high-voltage power supplies (2410, Keithley) triggered in sync by a waveform generator. The gate potential is tuned dynamically by using a voltage divider, as shown in Fig. S9 in the SI. Unless specified otherwise, we used an electrolytecomposed of 10 mM acetic acid and 1 mM NaOH (pH 3.8). In the streamline shaping experiments, we generated pressure driven flow by applying negative pressure to one of the reservoirs using a water column.

Time-averaged slip velocity
Let us consider the case of a uniform surface, having an embedded electrode (hereafter referred to as 'gate electrode'), covered with an electrolyte and subject to a periodic electric field ( ) is the potential on the driving electrode, placed at a distance L from the ground electrode. Here, φ ex is the amplitude of the potential, T is the frequency and ex T is the period. The gate electrode, placed at a distance el x from the ground electrode, is subject to a periodic potential where φ e is the amplitude of the potential, T is the frequency and el T is the period, Ω is the phase difference between ( ) and el C is a DC bias potential. We assume the electrode is small compared to the length of the channel L , and thus the potential in the liquid above the The electroosmotic flow velocity generated by the surface over the electrode is then given by the Helmholtz-Smoluchowski slip velocity where ε l and η are the dielectric permittivity and viscosity of the liquid respectively, and ( ) ζ t is the time variant zeta potential which is some function of the potential drop across the dielectric ( ) Substituting the value for ( ) E t and ( ) ζ t in Eq. S1 we obtain which when integrated over the lowest common multiple period lcm T yields the time averaged velocity 0 ( ) Here, we consider the simplified case where the electric fields and the zeta potentials have the same period = ω ω ω = el ex (assumed to be smaller than the inverse RC time scale of the electrical system 1 τ − RC ), and zero phase difference 0 Ω = , resulting in a maximal time-averaged EOF velocity (4). Further, we consider the case for the first and second half of the period, respectively). Defining the difference between the gate potential and the channel potential amplitudes as x L , and the difference between the DC bias on the gate potential and in the channel as where the superscripts / 2 T and T indicate the first and second half of the period, respectively. Thus the time averaged velocity (Eq. S4) is simply the arithmetic mean of the velocity of the two half periods ( ) The time averaged velocity is composed of two terms corresponding to an AC contribution which depends on the difference of the zeta potential values between the two half periods, and a DC component, which depends [S6]

Breakdown characterization
We characterized the dielectric breakdown of various dielectric materials and layer thickness using the configuration depicted in Fig. S2, in which an electrode immersed in a solution of 10 mM lactic acid and 5 mM NaOH (pH 3.7) is in contact with a grounded gate electrode (covered with the specific dielectric under study).

Fig. S2. Schematic of the experimental setup for the breakdown experiments. The dielectric deposited on top of a gate electrode is immersed in a buffer composed of 10 mM lactic acid and 5 mM NaOH (pH 3.7). We apply an electric field across the dielectric and monitor the current. The electric field is increased, until the dielectric breaks.
We apply an increasing ( 0 φ ∆ < ) 1 or decreasing ( 0 φ ∆ > ) potential with steps between 10 and 50 V every 3 s, while monitoring the I-V curve using a high voltage power supply (Keithley, 2410) controlled with Matlab (R2017, MathWorks). We observed two typical behaviors of the I-V curve. The first type, shown in Fig. S3 A, is characterized by a drastic increase of the current beyond a certain threshold, which we attribute to the dielectric breakdown. This type of behavior is common for SiO2 and therefore we define this response SiO2type. For this type, we define the breakdown value as the first voltage at which two subsequent measurements yield a current increase of more than 10-fold. The other type, shown in Fig. S3 B, is characterized by a smooth I-V We found this type of curves to be typical of SiN-based dielectrics, and thus we refer to them as SiN-type.  The current constantly increases, without abrupt change.
Whereas for the SiO2-type the value of the breakdown can be directly extract from the observation of the I-V curve, for the SiN-type we assessed the breakdown values performing a series of hysteresis cycles: for each voltage value being tested, we ramp the voltage in 1 V steps until reaching the tested voltage, and then ramp down the voltage at the same rate. We define the breakdown voltage as the lowest test voltage for which the ramp down curve no longer follows the ramp up curve. Fig S4 A and B show the two curves for a test voltage below (20 V) and after (40 V) breakdown, respectively. showing SiN-type are HfO3 + SiNx, Al2O3 + SiNx, SiO2 (ALD) + SiNx for the family of layers consisting of 20 nm deposited with ALD followed by 500 nm deposited with PECVD (Fig. S8) and SiN (500nn) deposited with PECVD ( Fig. 2 A in the main text).